Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

I. Min Liu, Tan Li Chou, Adnan Aziz, D. F. Wong

Research output: Contribution to conferencePaper

Abstract

We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) algorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.

Original languageEnglish (US)
Pages33-38
Number of pages6
StatePublished - Jan 1 2000
EventISPD-2000: International Symposium on Physical Design - San Diego, CA, USA
Duration: Apr 9 2000Apr 12 2000

Conference

ConferenceISPD-2000: International Symposium on Physical Design
CitySan Diego, CA, USA
Period4/9/004/12/00

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Liu, I. M., Chou, T. L., Aziz, A., & Wong, D. F. (2000). Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. 33-38. Paper presented at ISPD-2000: International Symposium on Physical Design, San Diego, CA, USA, .