Yield-Aware Interposer Design for UCIe Interconnects

Ram Krishna, Ashita Victor, Srujan Penta, Xu Chen, Muhannad S. Bakir, Nam Sung Kim, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents an interposer design methodol-ogy for UCle die-to-die interfaces that maximizes yield given a set of signal integrity specifications. Four different routing configurations on a silicon interposer are considered, and the cost, performance, and yield tradeoffs are elucidated. The fabrication steps for the D2D interconnects are outlined and sources of yield-limiting variability are identified. The yield analysis is expedited by the use of a Gaussian Process Regression surrogate model.

Original languageEnglish (US)
Title of host publication33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350351231
DOIs
StatePublished - 2024
Externally publishedYes
Event33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024 - Toronto, Canada
Duration: Oct 6 2024Oct 9 2024

Publication series

Name33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024

Conference

Conference33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024
Country/TerritoryCanada
CityToronto
Period10/6/2410/9/24

Keywords

  • UCle
  • crosstalk
  • heterogeneous integration
  • insertion loss
  • interposer
  • signal integrity
  • yield

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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