@inproceedings{248f552641604edfae7f0430ea12c6bd,
title = "Yield-Aware Interposer Design for UCIe Interconnects",
abstract = "This work presents an interposer design methodol-ogy for UCle die-to-die interfaces that maximizes yield given a set of signal integrity specifications. Four different routing configurations on a silicon interposer are considered, and the cost, performance, and yield tradeoffs are elucidated. The fabrication steps for the D2D interconnects are outlined and sources of yield-limiting variability are identified. The yield analysis is expedited by the use of a Gaussian Process Regression surrogate model.",
keywords = "UCle, crosstalk, heterogeneous integration, insertion loss, interposer, signal integrity, yield",
author = "Ram Krishna and Ashita Victor and Srujan Penta and Xu Chen and Bakir, {Muhannad S.} and Kim, {Nam Sung} and Elyse Rosenbaum",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024 ; Conference date: 06-10-2024 Through 09-10-2024",
year = "2024",
doi = "10.1109/EPEPS61853.2024.10753661",
language = "English (US)",
series = "33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024",
address = "United States",
}