Worst case delay analysis for memory interference in multicore systems

Rodolfo Pellizzoni, Andreas Schranzhofer, Jian Jia Chen, Marco Caccamo, Lothar Thiele

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.

Original languageEnglish (US)
Title of host publicationDATE 10 - Design, Automation and Test in Europe
Pages741-746
Number of pages6
StatePublished - Jun 9 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
CountryGermany
CityDresden
Period3/8/103/12/10

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Worst case delay analysis for memory interference in multicore systems'. Together they form a unique fingerprint.

Cite this