TY - GEN
T1 - Worst case delay analysis for memory interference in multicore systems
AU - Pellizzoni, Rodolfo
AU - Schranzhofer, Andreas
AU - Chen, Jian Jia
AU - Caccamo, Marco
AU - Thiele, Lothar
N1 - Funding Information:
We thank S. E. Harris, E. Knill, M. Lukin, S. Unlu, and I. Wilson-Rae for helpful discussions. This research is supported by the Humboldt Foundation. Additional support is provided by the Packard Foundation.
PY - 2010
Y1 - 2010
N2 - Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.
AB - Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.
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U2 - 10.1109/date.2010.5456952
DO - 10.1109/date.2010.5456952
M3 - Conference contribution
AN - SCOPUS:77953092559
SN - 9783981080162
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 741
EP - 746
BT - DATE 10 - Design, Automation and Test in Europe
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Y2 - 8 March 2010 through 12 March 2010
ER -