Workload-aware voltage regulator optimization for power efficient multi-core processors

Abhishek A. Sinkar, Hao Wang, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modern multi-core processors use power management techniques such as dynamic voltage and frequency scaling (DVFS) and clock gating (CG) which cause the processor to operate in various performance and power states depending on runtime workload characteristics. A voltage regulator (VR), which is designed to provide power to the processor at its highest performance level, can significantly degrade in efficiency when the processor operates in the deep power saving states. In this paper, we propose VR optimization techniques to improve the energy efficiency of the processor + VR system by using the workload dependent P- and C-state residency of real processors. Our experimental results for static VR optimization show up to 19%, 20%, and 4% reduction in energy consumption for workstation, mobile and server multi-core processors. We also investigate the effect of dynamically changing VR parameters on the energy efficiency compared to the static optimization.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Pages1134-1137
Number of pages4
StatePublished - May 24 2012
Externally publishedYes
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: Mar 12 2012Mar 16 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
CountryGermany
CityDresden
Period3/12/123/16/12

Keywords

  • C-state
  • DVFS
  • P-state
  • switching voltage regulator

ASJC Scopus subject areas

  • Engineering(all)

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