Work in progress: Identifying unexpected inter-core interference induced by shared cache

Denis Hoornaert, Shahin Roozkhosh, Renato Mancuso, Marco Caccamo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In modern real-time multicore systems, understanding and adequately managing shared caches is essential to ensure the temporal isolation of critical tasks. Recent research has identified and extensively studied the sources of unpredictability imputable to shared caches, heavily promoting techniques such as cache partitioning and internal resources management. In this article, we highlight the existence of an enigmatic source of inter-core interference: the CPU-brainfreeze. Experiments realized on a development board show that benchmarks (selected from the San-Diego Vision Benchmark Suite) can exhibit up to a 10-fold increase in their execution time. The same experiment shows that for extreme cases, the core cluster can be stalled indefinitely.

Original languageEnglish (US)
Title of host publicationProceedings - 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium, RTAS 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages517-520
Number of pages4
ISBN (Electronic)9781665403863
DOIs
StatePublished - May 2021
Externally publishedYes
Event27th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2021 - Virtual, Online
Duration: May 18 2021May 21 2021

Publication series

NameProceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
Volume2021-May
ISSN (Print)1545-3421

Conference

Conference27th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2021
CityVirtual, Online
Period5/18/215/21/21

Keywords

  • Multi-processors Systems
  • Non-blocking Shared Caches
  • Real-Time Systems

ASJC Scopus subject areas

  • Engineering(all)

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