Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs

Muhammad Khellah, Yibin Ye, Nam Sung Kim, Dinesh Somasekhar, Gunjan Pandya, Ali Farhang, Kevin Zhang, Clair Webb, Vivek De

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Pulsed Wordline (PWL) & Pulsed Bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15X while incurring <1% area overhead. Both PBL & PWL with Read-Modify-Write (PWL-RMW) provide the best improvements (26X) in cell stability, with significant area overheads (4-8%).

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages9-10
Number of pages2
StatePublished - Dec 1 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: Jun 15 2006Jun 17 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI
Period6/15/066/17/06

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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