@inproceedings{458dd04830954db5a20315a58380eb8f,
title = "Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs",
abstract = "Pulsed Wordline (PWL) & Pulsed Bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15X while incurring <1% area overhead. Both PBL & PWL with Read-Modify-Write (PWL-RMW) provide the best improvements (26X) in cell stability, with significant area overheads (4-8%).",
author = "Muhammad Khellah and Yibin Ye and Kim, {Nam Sung} and Dinesh Somasekhar and Gunjan Pandya and Ali Farhang and Kevin Zhang and Clair Webb and Vivek De",
year = "2006",
language = "English (US)",
isbn = "1424400066",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "9--10",
booktitle = "2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",
note = "2006 Symposium on VLSI Circuits, VLSIC ; Conference date: 15-06-2006 Through 17-06-2006",
}