Abstract
Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the underlying learning algorithms to generate word level assertions. A post processing of assertions is employed to remove redundant propositions. Experimental results on Ethernet MAC, I2C, and OpenRISC designs show that the generated word level assertions have higher expressiveness and readability than their corresponding bit level assertions.
Original language | English (US) |
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Article number | 6386611 |
Pages (from-to) | 210-217 |
Number of pages | 8 |
Journal | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
DOIs | |
State | Published - 2012 |
Event | 2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States Duration: Nov 5 2012 → Nov 8 2012 |
ASJC Scopus subject areas
- Software
- Computer Science Applications
- Computer Graphics and Computer-Aided Design