Word level feature discovery to enhance quality of assertion mining

Lingyi Liu, Chen Hsuan Lin, Shobha Vasudevan

Research output: Contribution to journalConference article

Abstract

Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the underlying learning algorithms to generate word level assertions. A post processing of assertions is employed to remove redundant propositions. Experimental results on Ethernet MAC, I2C, and OpenRISC designs show that the generated word level assertions have higher expressiveness and readability than their corresponding bit level assertions.

Original languageEnglish (US)
Article number6386611
Pages (from-to)210-217
Number of pages8
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - Dec 1 2012
Event2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
Duration: Nov 5 2012Nov 8 2012

Fingerprint

Static analysis
Ethernet
Dynamic analysis
Learning algorithms
Learning systems
Processing

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Word level feature discovery to enhance quality of assertion mining. / Liu, Lingyi; Lin, Chen Hsuan; Vasudevan, Shobha.

In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 01.12.2012, p. 210-217.

Research output: Contribution to journalConference article

@article{0cf837db04e0452d8b91b375429a3b72,
title = "Word level feature discovery to enhance quality of assertion mining",
abstract = "Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the underlying learning algorithms to generate word level assertions. A post processing of assertions is employed to remove redundant propositions. Experimental results on Ethernet MAC, I2C, and OpenRISC designs show that the generated word level assertions have higher expressiveness and readability than their corresponding bit level assertions.",
author = "Lingyi Liu and Lin, {Chen Hsuan} and Shobha Vasudevan",
year = "2012",
month = "12",
day = "1",
language = "English (US)",
pages = "210--217",
journal = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",
issn = "1092-3152",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Word level feature discovery to enhance quality of assertion mining

AU - Liu, Lingyi

AU - Lin, Chen Hsuan

AU - Vasudevan, Shobha

PY - 2012/12/1

Y1 - 2012/12/1

N2 - Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the underlying learning algorithms to generate word level assertions. A post processing of assertions is employed to remove redundant propositions. Experimental results on Ethernet MAC, I2C, and OpenRISC designs show that the generated word level assertions have higher expressiveness and readability than their corresponding bit level assertions.

AB - Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the underlying learning algorithms to generate word level assertions. A post processing of assertions is employed to remove redundant propositions. Experimental results on Ethernet MAC, I2C, and OpenRISC designs show that the generated word level assertions have higher expressiveness and readability than their corresponding bit level assertions.

UR - http://www.scopus.com/inward/record.url?scp=84872328581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84872328581&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:84872328581

SP - 210

EP - 217

JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

SN - 1092-3152

M1 - 6386611

ER -