WiSync: An architecture for fast synchronization through on-chip wireless communication

Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcon, Josep Torrellas

Research output: Contribution to journalArticlepeer-review

Abstract

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

Original languageEnglish (US)
Pages (from-to)3-17
Number of pages15
JournalACM SIGPLAN Notices
Volume51
Issue number4
DOIs
StatePublished - Apr 2016

Keywords

  • On-chip wireless communication
  • Synchronization

ASJC Scopus subject areas

  • Computer Science(all)

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