TY - GEN
T1 - WiSync
T2 - 21st International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016
AU - Abadal, Sergi
AU - Cabellos-Aparicio, Albert
AU - Alarcón, Eduard
AU - Torrellas, Josep
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/3/25
Y1 - 2016/3/25
N2 - In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, calledWiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128- threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization,WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.
AB - In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, calledWiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128- threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization,WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.
KW - On-chip wireless communication
KW - Synchronization
UR - http://www.scopus.com/inward/record.url?scp=84975222177&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84975222177&partnerID=8YFLogxK
U2 - 10.1145/2872362.2872396
DO - 10.1145/2872362.2872396
M3 - Conference contribution
AN - SCOPUS:84975222177
T3 - International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
SP - 3
EP - 17
BT - ASPLOS 2016 - 21st International Conference on Architectural Support for Programming Languages and Operating Systems
PB - Association for Computing Machinery
Y2 - 2 April 2016 through 6 April 2016
ER -