Wiring resource minimization for physically-complex Network-on-Chip architectures

Nickvash Kani, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Networks-on-Chip (NoCs) have been proposed to facilitate communication between the many cores present on a single chip. One important factor to consider when designing certain NoCs, such as the generalized hypercube, is the large wiring area requirement. The contributions of this paper are fourfold. First, a special interconnect sizing methodology is introduced and analyzed in the context of a 2D generalized-hypercube network. It is found that if the interconnects in a hypercube network are sized ideally, it would require roughly half the area that the default, single-wire-width case requires. Furthermore, factoring in the real world scenario where only a few distinct wire widths are available, the methodology presented in this paper would still save ≈ 35% of the wiring area. Second, interconnects constructed using two discrete wire widths are proposed. Using this dual-width sizing optimization, a 46% reduction in aggregate wiring area can be achieved. Third, the trade-off between wiring area and interconnect power dissipation has been quantified. Because it typically takes more repeaters to achieve the same delay with a thinner interconnect, these repeaters will cause the power consumption to increase. It is found that the sizing reduction causes a 33% link power increase for the ideal case. Lastly, it is shown that network topologies cannot be reliably compared without using the sizing methodologies shown in this paper.

Original languageEnglish (US)
Title of host publicationInternational System on Chip Conference
EditorsRamalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
PublisherIEEE Computer Society
Pages261-266
Number of pages6
ISBN (Electronic)9781479933785
DOIs
StatePublished - Nov 5 2014
Externally publishedYes
Event27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
Duration: Sep 2 2014Sep 5 2014

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference27th IEEE International System on Chip Conference, SOCC 2014
CountryUnited States
CityLas Vegas
Period9/2/149/5/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Wiring resource minimization for physically-complex Network-on-Chip architectures'. Together they form a unique fingerprint.

Cite this