Wire planning with bounded over-the-block wires

Hua Xiang, I. Min Liu, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory, while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.

Original languageEnglish (US)
Title of host publicationProceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005
Pages622-627
Number of pages6
DOIs
StatePublished - Dec 1 2005
Event6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA, United States
Duration: Mar 21 2005Mar 23 2005

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other6th International Symposium on Quality Electronic Design, ISQED 2005
Country/TerritoryUnited States
CitySan Jose, CA
Period3/21/053/23/05

Keywords

  • over-the-block
  • routing
  • wire planning

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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