TY - JOUR
T1 - Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters
AU - Bhat, Ritesh
AU - Zhou, Jin
AU - Krishnaswamy, Harish
N1 - Funding Information:
Manuscript received May 6, 2017; revised July 30, 2017 and September 24, 2017; accepted September 25, 2017. Date of publication November 8, 2017; date of current version November 21, 2017. This paper was approved by Guest Editor Alyosha Molnar. This work was supported by the DARPA RF-FPGA program. (Corresponding author: Harish Krishnaswamy.) R. Bhat and H. Krishnaswamy are with the Department of Electrical Engineering, Columbia University, New York, NY 10027 USA (e-mail: harish@ee.columbia.edu).
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2017/12
Y1 - 2017/12
N2 - A major drawback of digital transmitters (DTX) is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to radio frequency and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in frequency-division duplexing systems due to receiver desensitization or impose stringent coexistence challenges. In this paper, we describe a DTX that embeds mixed-domain multi-tap finite-impulse response (FIR) filtering with programmable analog sub-sample delays within a highly linear and mismatch-resilient switched-capacitor DTX architecture. It is shown that switched-capacitor power amplifiers (SCPA) in conjunction with transformer-based power combining are ideal candidates for embedding mixed-domain FIR filtering since the near-constant source impedance of the SCPA greatly aids in linear FIR summation thereby preserving the desired noise-shaping profile. Moreover, their excellent mismatch characteristics help in ensuring precise tap weights in the FIR which enhances noise suppression. The availability of multiple taps in this architecture also allows the synthesis of FIR configurations with wide notch bandwidths (BW). Theoretical analyses of this architecture and design trade-offs related to linearity, mismatch, output power, and efficiency are discussed. The implemented 65 nm CMOS prototype exhibits a peak output power of 30.3 dBm and a peak system efficiency of 34%, and achieves a noise floor of -149 dBc/Hz over a BW of 20 MHz at an offset of 135 MHz from a 2.23 GHz carrier while transmitting a 1.4 MHz 64-QAM signal with an average output power of 22 dBm.
AB - A major drawback of digital transmitters (DTX) is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to radio frequency and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in frequency-division duplexing systems due to receiver desensitization or impose stringent coexistence challenges. In this paper, we describe a DTX that embeds mixed-domain multi-tap finite-impulse response (FIR) filtering with programmable analog sub-sample delays within a highly linear and mismatch-resilient switched-capacitor DTX architecture. It is shown that switched-capacitor power amplifiers (SCPA) in conjunction with transformer-based power combining are ideal candidates for embedding mixed-domain FIR filtering since the near-constant source impedance of the SCPA greatly aids in linear FIR summation thereby preserving the desired noise-shaping profile. Moreover, their excellent mismatch characteristics help in ensuring precise tap weights in the FIR which enhances noise suppression. The availability of multiple taps in this architecture also allows the synthesis of FIR configurations with wide notch bandwidths (BW). Theoretical analyses of this architecture and design trade-offs related to linearity, mismatch, output power, and efficiency are discussed. The implemented 65 nm CMOS prototype exhibits a peak output power of 30.3 dBm and a peak system efficiency of 34%, and achieves a noise floor of -149 dBc/Hz over a BW of 20 MHz at an offset of 135 MHz from a 2.23 GHz carrier while transmitting a 1.4 MHz 64-QAM signal with an average output power of 22 dBm.
KW - Digital filters
KW - FET integrated circuits
KW - MOS integrated circuits
KW - RF transmitters
KW - digital integrated circuits
KW - finite-impulse response (FIR) filters
KW - high power amplifiers
KW - mixed analog digital integrated circuits
KW - nonlinear circuits
KW - notch filters
KW - predistortion
KW - radio frequency (RF) integrated circuits
KW - radio transmitters
KW - sampled data circuits
KW - switched-capacitor circuits
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U2 - 10.1109/JSSC.2017.2760899
DO - 10.1109/JSSC.2017.2760899
M3 - Article
AN - SCOPUS:85033681610
SN - 0018-9200
VL - 52
SP - 3405
EP - 3420
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 12
M1 - 8100710
ER -