TY - GEN
T1 - WeeFence
T2 - 40th Annual International Symposium on Computer Architecture, ISCA 2013
AU - Duan, Yuelu
AU - Muzahid, Abdullah
AU - Torrellas, Josep
PY - 2013
Y1 - 2013
N2 - Although fences are designed for low-overhead concurrency coordination, they can be expensive in current machines. If fences were largely free, faster fine-grained concurrent algorithms could be devised, and compilers could guarantee Sequential Consistency (SC) at little cost. In this paper, we present WeeFence (or WFence for short), a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only when an incorrect reordering of accesses is about to happen, does the hardware stall to prevent it. In the paper, we present the WFence design for TSO, and compare it to a conventional fence with speculation for 8-processor multicore simulations. We run parallel kernels that contain explicit fences and parallel applications that do not. For the kernels, WFence eliminates nearly all of the fence stall, reducing the kernels' execution time by an average of 11%. For the applications, a conservative compiler algorithm places fences in the code to guarantee SC. In this case, on average, WFences reduce the resulting fence overhead from 38% of the applications' execution time to 2% (in a centralized WFence design), or from 36% to 5% (in a distributed WFence design).
AB - Although fences are designed for low-overhead concurrency coordination, they can be expensive in current machines. If fences were largely free, faster fine-grained concurrent algorithms could be devised, and compilers could guarantee Sequential Consistency (SC) at little cost. In this paper, we present WeeFence (or WFence for short), a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only when an incorrect reordering of accesses is about to happen, does the hardware stall to prevent it. In the paper, we present the WFence design for TSO, and compare it to a conventional fence with speculation for 8-processor multicore simulations. We run parallel kernels that contain explicit fences and parallel applications that do not. For the kernels, WFence eliminates nearly all of the fence stall, reducing the kernels' execution time by an average of 11%. For the applications, a conservative compiler algorithm places fences in the code to guarantee SC. In this case, on average, WFences reduce the resulting fence overhead from 38% of the applications' execution time to 2% (in a centralized WFence design), or from 36% to 5% (in a distributed WFence design).
KW - Fences
KW - Memory Consistency
KW - Parallel Programming
KW - Sequential Consistency
KW - Shared-Memory Multiprocessors
KW - Synchronization
UR - http://www.scopus.com/inward/record.url?scp=84881136189&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881136189&partnerID=8YFLogxK
U2 - 10.1145/2485922.2485941
DO - 10.1145/2485922.2485941
M3 - Conference contribution
AN - SCOPUS:84881136189
SN - 9781450320795
T3 - Proceedings - International Symposium on Computer Architecture
SP - 213
EP - 224
BT - ISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Y2 - 23 June 2013 through 27 June 2013
ER -