WeeFence: Toward making fences free in TSO

Yuelu Duan, Abdullah Muzahid, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Although fences are designed for low-overhead concurrency coordination, they can be expensive in current machines. If fences were largely free, faster fine-grained concurrent algorithms could be devised, and compilers could guarantee Sequential Consistency (SC) at little cost. In this paper, we present WeeFence (or WFence for short), a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only when an incorrect reordering of accesses is about to happen, does the hardware stall to prevent it. In the paper, we present the WFence design for TSO, and compare it to a conventional fence with speculation for 8-processor multicore simulations. We run parallel kernels that contain explicit fences and parallel applications that do not. For the kernels, WFence eliminates nearly all of the fence stall, reducing the kernels' execution time by an average of 11%. For the applications, a conservative compiler algorithm places fences in the code to guarantee SC. In this case, on average, WFences reduce the resulting fence overhead from 38% of the applications' execution time to 2% (in a centralized WFence design), or from 36% to 5% (in a distributed WFence design).

Original languageEnglish (US)
Title of host publicationISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Number of pages12
StatePublished - Aug 12 2013
Event40th Annual International Symposium on Computer Architecture, ISCA 2013 - Tel-Aviv, Israel
Duration: Jun 23 2013Jun 27 2013

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Other40th Annual International Symposium on Computer Architecture, ISCA 2013


  • Fences
  • Memory Consistency
  • Parallel Programming
  • Sequential Consistency
  • Shared-Memory Multiprocessors
  • Synchronization

ASJC Scopus subject areas

  • Hardware and Architecture


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