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Wear-out simulation environment for VLSI designs
Gwan S. Choi
,
Ravishankar K Iyer
Electrical and Computer Engineering
National Center for Supercomputing Applications (NCSA)
Carl R. Woese Institute for Genomic Biology
Coordinated Science Lab
Information Trust Institute
Biomedical and Translational Sciences
Siebel School of Computing and Data Science
Center for Global Studies
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Keyphrases
Simulation Environment
100%
Wearout
100%
VLSI Design
100%
Circuit Simulation
50%
Technology Effect
50%
Device Level
50%
Monte Carlo Simulation
50%
Custom Design
50%
Device Dimensions
50%
Electromigration
50%
Dimensionality Reduction
50%
Importance Sampling
50%
Reliability Prediction
50%
Event Sequences
50%
Fabrication Technology
50%
Failure Mode
50%
Monte Carlo Analysis
50%
Operating Voltage
50%
Technology Parameters
50%
Reliability Assessment
50%
VLSI Systems
50%
Switch Level
50%
Dynamic Sequence
50%
Oxide Breakdown
50%
Operating Environment
50%
Time-to-failure Distribution
50%
Weak Location
50%
VLSI chip
50%
Simulation-based Approach
50%
Microprocessor chips
50%
Improved Technology
50%
Environmental Technology
50%
Engineering
Failure Mode
100%
Circuit Simulation
100%
Microprocessor Chips
100%
Operating Voltage
100%
Electromigration
100%
Monte Carlo Analysis
100%
Simulation Environment
100%
Run Length
100%
Reliability Assessment
100%
Reliability Prediction
100%
Operating Environment
100%
Level Switch
100%