Abstract

This paper introduces a new simulation-based approach for the reliability prediction of VLSI designs. The approach combines the switch-level circuit simulation and the device-level Monte Carlo simulation to achieve a realistic reliability assessment. The Monte Carlo analysis makes use of importance sampling to reduce the run lengths. Key advantages of this approach are that it can closely mimic dynamic sequences of events in a device over time, localize the weak locations/aspects of a target chip, and generate time-to-failure (TTF) distribution for an entire VLSI chip. In the current implementation, two common IC failure modes (electromigration and oxide breakdown) are simultaneously simulated under varying operating environments and fabrication technology parameters. In particular, operating voltage, temperature and the device dimension are varied and, the impact of technology improvements, such as reduced dimension on reliability, is quantified. The use of this environment for developing reliable VLSI systems is illustrated with a case study of a custom-designed microprocessor chip.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Symposium on Fault-Tolerant Computing
Editors Anon
PublisherPubl by IEEE
Pages320-329
Number of pages10
ISBN (Print)0818636823
StatePublished - Dec 1 1993
EventProceedings of the 23rd International Symposium on Fault-Tolerant Computing - Toulouse, Fr
Duration: Jun 22 1993Jun 24 1993

Publication series

NameDigest of Papers - International Symposium on Fault-Tolerant Computing
ISSN (Print)0731-3071

Other

OtherProceedings of the 23rd International Symposium on Fault-Tolerant Computing
CityToulouse, Fr
Period6/22/936/24/93

ASJC Scopus subject areas

  • Hardware and Architecture

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