Weak ordering - a new definition

Sarita V. Adve, Mark D. Hill

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequenfiaf consisfency. This model guaranteest hat all memory accessesw ill appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. Weak ordering was first defined by Dubois, Scheurich and Briggs in terms of a set of rules for hardware that have to be made visible to software. The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than having to think about weaker memory. or even write buffers. Following this hypothesis, we re-define weak ordering as a contract between software and hardware. By this contract. software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent to at least the software that obeys those constraints. We illusuate the power of the new definition with a set of software constraints that forbid data races and an implementation for cache-coherent systems that is not allowed by the old definition.

Original languageEnglish (US)
Title of host publicationISCA 1998 - 25 years of the International Symposia on Computer Architecture (Selected Papers)
EditorsGurindar S. Sohi
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages363-375
Number of pages13
ISBN (Electronic)9781581130584
DOIs
StatePublished - Aug 1 1998
Externally publishedYes
Event25th International Symposium on Computer Architecture, ISCA 1998 - Barcelona, Spain
Duration: Jun 27 1998Jul 2 1998

Publication series

NameProceedings - International Symposium on Computer Architecture
Volume1998-June
ISSN (Print)1063-6897

Conference

Conference25th International Symposium on Computer Architecture, ISCA 1998
Country/TerritorySpain
CityBarcelona
Period6/27/987/2/98

Keywords

  • sequential consistency
  • shared-memory multiprocessor
  • weak ordering

ASJC Scopus subject areas

  • Hardware and Architecture

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