TY - GEN
T1 - Weak ordering--A new definition
AU - Adve, Sarita V.
AU - Hill, Mark D.
PY - 1990
Y1 - 1990
N2 - A memory model for a shared-memory multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency, which guarantees that all memory accesses will appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than have to think about weaker memory, or even write buffers. Following this hypothesis, weak ordering is defined as a contract between software and hardware. By this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent, at least to the software that obeys those constraints. The authors illustrate the power of the new definition with a set of software constraints that forbid data races and with an implementation for cache-coherent systems that is not allowed by the old definition.
AB - A memory model for a shared-memory multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency, which guarantees that all memory accesses will appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than have to think about weaker memory, or even write buffers. Following this hypothesis, weak ordering is defined as a contract between software and hardware. By this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent, at least to the software that obeys those constraints. The authors illustrate the power of the new definition with a set of software constraints that forbid data races and with an implementation for cache-coherent systems that is not allowed by the old definition.
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U2 - 10.1145/325164.325100
DO - 10.1145/325164.325100
M3 - Conference contribution
AN - SCOPUS:0025433676
SN - 0818620471
SN - 9780818620478
T3 - Conference Proceedings - Annual Symposium on Computer Architecture
SP - 2
EP - 14
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - Publ by IEEE
T2 - Proceedings of the 17th Annual International Symposium on Computer Architecture
Y2 - 28 May 1990 through 31 May 1990
ER -