Weak ordering--A new definition

Sarita V. Adve, Mark D. Hill

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A memory model for a shared-memory multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency, which guarantees that all memory accesses will appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than have to think about weaker memory, or even write buffers. Following this hypothesis, weak ordering is defined as a contract between software and hardware. By this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent, at least to the software that obeys those constraints. The authors illustrate the power of the new definition with a set of software constraints that forbid data races and with an implementation for cache-coherent systems that is not allowed by the old definition.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Pages2-14
Number of pages13
ISBN (Print)0818620471, 9780818620478
DOIs
StatePublished - Jan 1 1990
Externally publishedYes
EventProceedings of the 17th Annual International Symposium on Computer Architecture - Seattle, WA, USA
Duration: May 28 1990May 31 1990

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture
ISSN (Print)0149-7111

Other

OtherProceedings of the 17th Annual International Symposium on Computer Architecture
CitySeattle, WA, USA
Period5/28/905/31/90

ASJC Scopus subject areas

  • Engineering(all)

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