WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence

Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha, Heechul Yun

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed, meaning that: (1) current industrial engineering processes cannot be reused, (2) software developed and certified for single-core chips cannot be deployed on multi-core platforms as is. In this work, we propose the Single Core Equivalence (SCE) technology: a framework of OS-level techniques designed for commercial (COTS) architectures that exports a set of equivalent single-core virtual machines from a multi-core platform. This allows per-core schedulability results to be calculated in isolation and to hold when multiple cores of the system run in parallel. Thus, SCE allows each core of a multi-core chip to be considered as a conventional single-core chip, ultimately enabling industry to reuse existing software, schedulability analysis methodologies and engineering processes.

Original languageEnglish (US)
Title of host publicationProceedings - 27th Euromicro Conference on Real-Time Systems, ECRTS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)9781467375702
StatePublished - Aug 3 2015
Event27th Euromicro Conference on Real-Time Systems, ECRTS 2015 - Lund, Sweden
Duration: Jul 7 2015Jul 10 2015

Publication series

NameProceedings - Euromicro Conference on Real-Time Systems
ISSN (Print)1068-3070


Other27th Euromicro Conference on Real-Time Systems, ECRTS 2015

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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