TY - GEN
T1 - Vulcan
T2 - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
AU - Muzahid, Abdullah
AU - Qi, Shanxiang
AU - Torrellas, Josep
PY - 2012
Y1 - 2012
N2 - Past work has focused on detecting data races as proxies for Sequential Consistency (SC) violations. However, most data races do not violate SC. In addition, lock-free data structures and synchronization libraries sometimes explicitly employ data races but rely on SC semantics for correctness. Consequently, to uncover SC violations, we need to develop a more precise technique. This paper presents Vulcan, the first hardware scheme to precisely detect SC violations at runtime, in programs running on a relaxed-consistency machine. The scheme leverages cache coherence protocol transactions to dynamically detect cycles in memory access orders across threads. When one such cycle is about to occur, an exception is triggered. For the conditions considered in this paper and with enough hardware, Vulcan suffers neither false positives nor false negatives. In addition, Vulcan induces negligible execution overhead, requires no help from the software, and only takes as input the program executable. Experimental results show that Vulcan detects three new SC violation bugs in the Pthread and Crypt libraries, and in the fmm code from SPLASH-2. Moreover, Vulcan's negligible execution overhead makes it suitable for on-the-fly use.
AB - Past work has focused on detecting data races as proxies for Sequential Consistency (SC) violations. However, most data races do not violate SC. In addition, lock-free data structures and synchronization libraries sometimes explicitly employ data races but rely on SC semantics for correctness. Consequently, to uncover SC violations, we need to develop a more precise technique. This paper presents Vulcan, the first hardware scheme to precisely detect SC violations at runtime, in programs running on a relaxed-consistency machine. The scheme leverages cache coherence protocol transactions to dynamically detect cycles in memory access orders across threads. When one such cycle is about to occur, an exception is triggered. For the conditions considered in this paper and with enough hardware, Vulcan suffers neither false positives nor false negatives. In addition, Vulcan induces negligible execution overhead, requires no help from the software, and only takes as input the program executable. Experimental results show that Vulcan detects three new SC violation bugs in the Pthread and Crypt libraries, and in the fmm code from SPLASH-2. Moreover, Vulcan's negligible execution overhead makes it suitable for on-the-fly use.
KW - Bug
KW - Memory model
KW - Parallel program
KW - Sequential consistency violation
UR - http://www.scopus.com/inward/record.url?scp=84876578479&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876578479&partnerID=8YFLogxK
U2 - 10.1109/MICRO.2012.41
DO - 10.1109/MICRO.2012.41
M3 - Conference contribution
AN - SCOPUS:84876578479
SN - 9780769549248
T3 - Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
SP - 363
EP - 375
BT - Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
Y2 - 1 December 2012 through 5 December 2012
ER -