Voltage monitor circuit for ESD diagnosis

Nathan Jack, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A newly designed on-chip voltage monitor circuit (VM) is capable of recording for subsequent readout the peak voltage reached at internal nodes during ESD events. Real-time voltage probing techniques during wafer-level CDM are verified using VMs; guidelines are discussed for reducing the impact of probing on current flow.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011
StatePublished - Nov 10 2011
Event2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011 - Anaheim, CA, United States
Duration: Sep 11 2011Sep 16 2011

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Other

Other2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011
CountryUnited States
CityAnaheim, CA
Period9/11/119/16/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Voltage monitor circuit for ESD diagnosis'. Together they form a unique fingerprint.

Cite this