Voltage clamping requirements for ESD protection of inputs in 90nm CMOS technology

Keyphrases

• 90-nm CMOS Technology 100%
• Breakdown Voltage 50%
• Circuit Design 50%
• Circuitry 50%
• Dielectric Breakdown Voltage 50%
• ESD Protection 100%
• Gate Dielectric 50%
• Gate Dielectric Breakdown 50%
• Input Circuit 50%
• Input Transistor 50%
• Performance Degradation 50%
• Voltage Clamp 100%

Engineering

• Breakdown Voltage 100%
• Circuit Design 50%
• Gate Dielectric 100%
• Input Transistor 50%
• Performance Degradation 50%