Abstract
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
| Original language | English (US) |
|---|---|
| Article number | 4772114 |
| Pages (from-to) | 50-58 |
| Number of pages | 9 |
| Journal | Electrical Overstress/Electrostatic Discharge Symposium Proceedings |
| State | Published - 2008 |
| Event | 2008 30th Annual on Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2008 - Tucson, AZ, United States Duration: Sep 7 2008 → Sep 12 2008 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering