Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips

Sheng Han Yeh, Jia Wen Chang, Tsung Wei Huang, Shang Tsung Yu, Tsung Yi Ho

Research output: Contribution to journalArticlepeer-review

Abstract

Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). Reliability is a critical factor in the design flow of EWOD chips, it directly affects the execution of bioassays. The trapped charge problem is the major factor degrading chip reliability, and this problem is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of the applied voltage. Except for the trapped charge problem, the wire routing required to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. However, previous research has failed to address the problems of excessive applied voltage and wire routing. Therefore, the resulting chip is more likely to fail during execution or cannot be realized because of the wire routing problem. A network-flow-based algorithm for reliability-driven pin-constrained EWOD chips is presented in this paper. The proposed algorithm not only minimizes the reliability problem induced by signal merging, but also prevents the operational failure caused by inappropriate addressing results. The proposed algorithm also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of the proposed algorithm on real-life chips.

Original languageEnglish (US)
Article number6879609
Pages (from-to)1302-1315
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume33
Issue number9
DOIs
StatePublished - Sep 2014

Keywords

  • Digital microfluidics
  • electrode addressing
  • reliability
  • wire routing.

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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