We present the following in this paper: 1) system design issues for the implementation of 51.84 Mb/s ATM-LAN and broadband access transceivers and 2) a pipelined fractionally spaced linear equalizer (FSLE) architecture. Algorithmic concerns such as signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints such as power dissipation, area, and speed were addressed in a common framework. The first step is to obtain a thorough understanding of major channel impairments. For the LAN environment, these include near-end crosstalk (NEXT), intersymbol interference (ISI), and impulse noise. The broadband access environment suffers from far-end crosstalk (FEXT), ISI, radio-frequency interference (RFI), impulse noise, and splitter losses. Measured characteristics of the channel are compared with analytical models. These are then employed in the design of the transmitter and receiver algorithms. The carrierless amplitude/phase (CAP) transmission scheme is presented as a practical bandwidth-efficient scheme for these applications. An adaptive FSLE employed in a CAP receiver eliminates ISI, suppresses NEXT (in case of ATM-LAN) and FEXT (in case of broadband access), and provides robustness to timing jitter. However, fractional tap spacing in combination with the highdata rates results in a high sample rate adaptive computation. Fortunately, throughput enhancing techniques such as pipelining can be employed for high-speed and low-power operation. A hardware-efficient pipelined architecture for the adaptive FSLE equalizer is presented. This architecture has been developed via the technique of relaxed look-ahead, which maintains the algorithm functionality rather than the input-output mapping. Simulation and experimental results for high-speed digital CAP transceivers for LAN and broadband access are also presented.
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering