VLSI systems design for 51.84 Mb/s ATM-LAN

Presented in this paper are: 1.) system design issues for the implementation of 51.84 Mb/s ATM-LAN transceivers, 2.) an integrated VLSI design methodology underlying this design, and 3.) a pipelined fractionally-spaced linear equalizer (FSLE) architecture. The integrated design methodology incorporates algorithmic concerns such as signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints such as power dissipation, area, and speed, within a common framework. Characteristics of the channel and the modulation scheme are described. An adaptive FSLE, employed in the receiver, eliminates ISI, suppresses NEXT (in case of ATM-LAN) and provides robustness to timing jitter. A pipelined FSLE architecture is derived via the relaxed look-ahead technique for high-sample rate adaptation. Simulation and experimental results for high-speed digital CAP transceivers for LAN are also presented.