VLSI systems design for 51.84 Mb/s ATM-LAN

Gi Hong Im, Naresh R. Shanbhag

Research output: Contribution to journalConference articlepeer-review

Abstract

Presented in this paper are: 1.) system design issues for the implementation of 51.84 Mb/s ATM-LAN transceivers, 2.) an integrated VLSI design methodology underlying this design, and 3.) a pipelined fractionally-spaced linear equalizer (FSLE) architecture. The integrated design methodology incorporates algorithmic concerns such as signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints such as power dissipation, area, and speed, within a common framework. Characteristics of the channel and the modulation scheme are described. An adaptive FSLE, employed in the receiver, eliminates ISI, suppresses NEXT (in case of ATM-LAN) and provides robustness to timing jitter. A pipelined FSLE architecture is derived via the relaxed look-ahead technique for high-sample rate adaptation. Simulation and experimental results for high-speed digital CAP transceivers for LAN are also presented.

Original languageEnglish (US)
Pages (from-to)2128-2131
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - Jan 1 1997
Externally publishedYes
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: Jun 9 1997Jun 12 1997

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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