In this paper, we present a VLSI implementation of an energy-efficient digital filtering algorithm developed using the soft DSP framework. Soft DSP refers to overscaling the supply voltage without sacrificing speed and employing algorithmic error-control to restore the resulting performance degradation. It is shown that delay imbalance at the circuit level inherent in existing arithmetic structures result in improved energy savings with marginal degradation in performance. The proposed scheme implemented in 0.35 μm TSMC technology provides an overall energy savings of up to 76% with performance degradation of less than 1dB in the signal-to-noise ratio (SNRo) at the filter output.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - 2000|
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