The NYU Ultracomputer architecture, a shared-memory MIMD parallel machine composed of thousands of processing elements, requires a high-performance interconnection network to approximate the ideal behavior of J. T. Schwartz's paracomputer model (1980) and to implement the fetch-and-add synchronization primitive efficiently. The authors describe the routing scheme and protocols for an enhanced message switching network and a VLSI implementation of a network node. Systolic queues at each node combine accesses to the same memory location by different processing elements allowing them to be performed in the same memory cycle. There have been encouraging results to date toward the goal of attaining network latency comparable with memory access times.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - Dec 1 1985|
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