VLSI architectures for soft-decision decoding of Reed-Solomon codes

Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag

Research output: Contribution to journalConference articlepeer-review

Abstract

In this paper, we present architectures for bivariate polynomial interpolation and factorization; the two main steps in algebraic soft-decision decoding of Reed-Solomon codes. We present an efficient formulation of the interpolation algorithm in which dependencies among the discrepancy coefficient computations are utilized to reduce interpolation complexity. Interpolation and factorization complexity is also reduced by using an FFT-like formulation for univariate polynomial translation. The modifications required to incorporate recently proposed algorithm level modifications for efficient interpolation and factorization are also presented. We determine the latency and hardware requirements for soft-decoding a [255, 239] Reed-Solomon code using the proposed architectures.

Original languageEnglish (US)
Pages (from-to)2584-2590
Number of pages7
JournalIEEE International Conference on Communications
Volume5
DOIs
StatePublished - Jan 1 2004
Event2004 IEEE International Conference on Communications - Paris, France
Duration: Jun 20 2004Jun 24 2004

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'VLSI architectures for soft-decision decoding of Reed-Solomon codes'. Together they form a unique fingerprint.

Cite this