Abstract
A pipelined finite-field multiplier structure in conjunction with a single systolic array implementation of the Berlekamp-Massey algorithm leads to a highly parallel decoder architecture in which the critical path delay is an order of magnitude smaller than the path delays of conventional architectures.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 419 |
| Number of pages | 1 |
| Journal | IEEE International Symposium on Information Theory - Proceedings |
| State | Published - 2000 |
| Event | 2000 IEEE International Symposium on Information Theory - Serrento, Italy Duration: Jun 25 2000 → Jun 30 2000 |
ASJC Scopus subject areas
- Theoretical Computer Science
- Information Systems
- Modeling and Simulation
- Applied Mathematics