Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

Carlton M. Osburn, Indong Kim, Sungkee Han, Indranil De, Kam F. Yee, Shyam Gannavaram, Sung Joo Lee, Chung Ho Lee, Zhijiong J. Luo, Wenjuan Zhu, John R. Hauser, Dim Lee Kwong, Gerald Lucovsky, T. P. Ma, Mehmet C. Öztürk

Research output: Contribution to journalReview article

Abstract

The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT) - for example, HfO2, ZrO2, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼105 A/cm2). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.

Original languageEnglish (US)
Pages (from-to)299-315
Number of pages17
JournalIBM Journal of Research and Development
Volume46
Issue number2-3
DOIs
StatePublished - Jan 1 2002
Externally publishedYes

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Osburn, C. M., Kim, I., Han, S., De, I., Yee, K. F., Gannavaram, S., Lee, S. J., Lee, C. H., Luo, Z. J., Zhu, W., Hauser, J. R., Kwong, D. L., Lucovsky, G., Ma, T. P., & Öztürk, M. C. (2002). Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? IBM Journal of Research and Development, 46(2-3), 299-315. https://doi.org/10.1147/rd.462.0299