Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits

Sungwoo Nam, Xiaocheng Jiang, Qihua Xiong, Donhee Ham, Charles M. Lieber

Research output: Contribution to journalArticlepeer-review

Abstract

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V out) versus input (Vin) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of ≈45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Original languageEnglish (US)
Pages (from-to)21035-21038
Number of pages4
JournalProceedings of the National Academy of Sciences of the United States of America
Volume106
Issue number50
DOIs
StatePublished - Dec 15 2009

Keywords

  • 3D
  • Integrated circuits
  • Multilayer assembly
  • Nanoelectronics

ASJC Scopus subject areas

  • General

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