TY - JOUR
T1 - Verifying nonlinear analog and mixed-signal circuits with inputs
AU - Fan, Chuchu
AU - Meng, Yu
AU - Maier, Jürgen
AU - Bartocci, Ezio
AU - Mitra, Sayan
AU - Schmid, Ulrich
N1 - Publisher Copyright:
© 2018
PY - 2018/1/1
Y1 - 2018/1/1
N2 - We present a new technique for verifying nonlinear and hybrid models with inputs. We observe that once an input signal is fixed, the sensitivity analysis of the model can be computed much more precisely. Based on this result, we propose a new simulation-driven verification algorithm and apply it to a suite of nonlinear and hybrid models of CMOS digital circuits under different input signals. The models are low-dimensional but with highly nonlinear ODEs, with nearly hundreds of logarithmic and exponential terms. Some of our experiments analyze the metastability of bistable circuits with very sensitive ODEs and rigorously establish the connection between metastability recovery time and sensitivity.
AB - We present a new technique for verifying nonlinear and hybrid models with inputs. We observe that once an input signal is fixed, the sensitivity analysis of the model can be computed much more precisely. Based on this result, we propose a new simulation-driven verification algorithm and apply it to a suite of nonlinear and hybrid models of CMOS digital circuits under different input signals. The models are low-dimensional but with highly nonlinear ODEs, with nearly hundreds of logarithmic and exponential terms. Some of our experiments analyze the metastability of bistable circuits with very sensitive ODEs and rigorously establish the connection between metastability recovery time and sensitivity.
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U2 - 10.1016/j.ifacol.2018.08.041
DO - 10.1016/j.ifacol.2018.08.041
M3 - Article
AN - SCOPUS:85052610853
SN - 2405-8963
VL - 51
SP - 241
EP - 246
JO - 6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018: Oxford, United Kingdom, 11—13 July 2018
JF - 6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018: Oxford, United Kingdom, 11—13 July 2018
IS - 16
ER -