VEBoC: Variation and error-aware design for billions of devices on a chip

Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandras Papakonstantinou, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues. We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore. We also present some of our insights for future reliable computing.

Original languageEnglish (US)
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages803-808
Number of pages6
DOIs
StatePublished - 2008
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: Mar 21 2008Mar 24 2008

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Country/TerritoryKorea, Republic of
CitySeoul
Period3/21/083/24/08

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'VEBoC: Variation and error-aware design for billions of devices on a chip'. Together they form a unique fingerprint.

Cite this