Variation-tolerant motion estimation architecture

Girish V. Varatkar, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference (MSAD) block is employed for detecting and correcting errors in the MSAD block. This architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio (PSNR) of ISR-ANT architecture increases by up to 1.8dB over that of the conventional architecture in 130nm IBM process technology. Furthermore, the PSNR variation is also reduced by 7× over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.

Original languageEnglish (US)
Title of host publication2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages126-131
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China
Duration: Oct 17 2007Oct 19 2007

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
CountryChina
CityShanghai
Period10/17/0710/19/07

Keywords

  • Error resiliency
  • Process variation

ASJC Scopus subject areas

  • Media Technology
  • Signal Processing

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    Varatkar, G. V., & Shanbhag, N. R. (2007). Variation-tolerant motion estimation architecture. In 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings (pp. 126-131). [4387531] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2007.4387531