Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC

Girish V. Varatkar, Sriram Narayanan, Naresh R Shanbhag, Douglas L Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Presented in this paper is an energy-efficient and variation-tolerant PN-code acquisition architecture for the wireless CDMA2000 standard. The architectures is based on the recently proposed stochastic sensor network-on-chip (SSNOC) computational paradigm [5]. The latter employs the principles of statistically similar decomposition and robust estimation theory to compensate for timing errors due to process variations. Performance of the SSNOC-based PN-code acquisition architecture at the slow process corner indicates that the average probability of detection PDet improves by up to 3 orders-of-magnitude over that of the conventional architecture, while the variation in PDet (σ/μ) is reduced by up to 2 orders-of-magnitude over that of the conventional architecture while simultaneously achieving a power reduction of 39%.

Original languageEnglish (US)
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages380-383
Number of pages4
DOIs
StatePublished - Sep 24 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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