Variation-conscious formal timing verification in RTL

Keyphrases

• Register Transfer Level 100%
• Timing Verification 100%
• SHARPE 50%
• Source Code 16%
• Circuit Level 16%
• Statistical Techniques 16%
• Static Analysis 16%
• Level Description 16%
• Design Decisions 16%
• Sources of Variation 16%
• Module Level 16%
• Embedded Processor 16%
• Design Cycle 16%
• Input Variability 16%
• Systematic Methodology 16%
• Delay Distribution 16%
• Probabilistic Model Checking 16%
• Discrete-time Markov Chain 16%
• Probabilistic Model Checker 16%
• OR1200 16%
• Compositional Reasoning 16%
• Post-synthesis 16%
• Statistical Delay 16%
• Design Correctness 16%
• Simulation Costs 16%
• Block Level 16%
• Synthesis Simulation 16%

Computer Science

• Register-Transfer Level 100%
• Timing Verification 100%
• Open Source 16%
• Statistical Technique 16%
• Analysis Technique 16%
• Source Codes 16%
• Level Description 16%
• discrete-time 16%
• Model Checking 16%
• model checker 16%
• Static Program Analysis 16%
• Timing Analysis 16%
• Embedded Processor 16%
• Time Markov Chain 16%
• Systematic Methodology 16%
• Datapath 16%
• Statistical Computing 16%
• Delay Distribution 16%