Variation aware routing for three-dimensional FPGAs

Chen Dong; Scott Chilstedt; Deming Chen

doi:10.1109/ISVLSI.2009.44

Variation aware routing for three-dimensional FPGAs

Chen Dong, Scott Chilstedt, Deming Chen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To maximize the potential of three-dimensional integrated circuit architectures, 3D CAD tools must be developed that are on-par with their 2D counterparts. In this paper, we present a statistical static timing analysis (SSTA) engine designed to deal with both the uncorrelated and correlated variations in 3D FPGAs. We consider the effects of intra-die and inter-die variation. Using the 3D physical design tool TPR as a base, we develop a new 3D routing algorithm which improves the average performance of two layer designs by over 22% and three layer designs by over 27%. To the best of our knowledge, this is the first physical design tool to consider variation in the routing and timing analysis of 3D FPGAs.

Original language	English (US)
Title of host publication	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Pages	298-303
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2009.44
State	Published - 2009
Event	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 - Tampa, FL, United States Duration: May 14 2009 → May 15 2009

Publication series

Name	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Other

Other	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Country/Territory	United States
City	Tampa, FL
Period	5/14/09 → 5/15/09

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

Online availability

10.1109/ISVLSI.2009.44

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Variation aware routing for three-dimensional FPGAs. / Dong, Chen; Chilstedt, Scott; Chen, Deming.
Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009. 2009. p. 298-303 5076424 (Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, C, Chilstedt, S & Chen, D 2009, Variation aware routing for three-dimensional FPGAs. in Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009., 5076424, Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp. 298-303, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, Tampa, FL, United States, 5/14/09. https://doi.org/10.1109/ISVLSI.2009.44

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Variation aware routing for three-dimensional FPGAs

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