Variation-aware layout-driven scheduling for performance yield optimization

With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move to deep submicron processes has led to increased levels of process variation, which must be considered during synthesis so that the performance yield of the circuit meets design specifications. In this paper, we tackle the problem of performance yield optimization during the scheduling task of high-level synthesis. We formulate the problem of performance yield optimization for scheduling as an integer linear programming problem (ILP) and offer the following contributions: 1) a totally unimodular ILP formulation for performance yield maximization and 2) a variation-aware and layout-driven iterative algorithm for performance yield improvement. Experimental results show that we can obtain significant gain in performance yield compared to a state-ofthe-art variation-aware high-level synthesis tool FastYield.