Variation-aware application scheduling and power management for chip multiprocessors

Radu Teodorescu, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for application scheduling and power management. One such power management algorithm., called LinOpt, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP -maximizing throughput at a given power budget. In a 20-core CMP, the combination of variation-aware application scheduling and LinOpt increases the average throughput by 12-17% and reduces the average ED2 by 30-38% -all relative to using variation-aware scheduling together with a simple extension to Intel's Foxton power management algorithm.

Original languageEnglish (US)
Title of host publicationISCA 2008, Proceedings - 35th International Symposium on Computer Architecture
Pages363-374
Number of pages12
DOIs
StatePublished - Oct 1 2008
EventISCA 2008, 35th International Symposium on Computer Architecture - Beijing, China
Duration: Jun 21 2008Jun 25 2008

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

OtherISCA 2008, 35th International Symposium on Computer Architecture
CountryChina
CityBeijing
Period6/21/086/25/08

ASJC Scopus subject areas

  • Hardware and Architecture

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