TY - GEN
T1 - Variation-aware application scheduling and power management for chip multiprocessors
AU - Teodorescu, Radu
AU - Torrellas, Josep
PY - 2008
Y1 - 2008
N2 - Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for application scheduling and power management. One such power management algorithm., called LinOpt, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP -maximizing throughput at a given power budget. In a 20-core CMP, the combination of variation-aware application scheduling and LinOpt increases the average throughput by 12-17% and reduces the average ED2 by 30-38% -all relative to using variation-aware scheduling together with a simple extension to Intel's Foxton power management algorithm.
AB - Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for application scheduling and power management. One such power management algorithm., called LinOpt, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP -maximizing throughput at a given power budget. In a 20-core CMP, the combination of variation-aware application scheduling and LinOpt increases the average throughput by 12-17% and reduces the average ED2 by 30-38% -all relative to using variation-aware scheduling together with a simple extension to Intel's Foxton power management algorithm.
UR - http://www.scopus.com/inward/record.url?scp=52649107085&partnerID=8YFLogxK
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U2 - 10.1109/ISCA.2008.40
DO - 10.1109/ISCA.2008.40
M3 - Conference contribution
AN - SCOPUS:52649107085
SN - 9780769531748
T3 - Proceedings - International Symposium on Computer Architecture
SP - 363
EP - 374
BT - ISCA 2008, Proceedings - 35th International Symposium on Computer Architecture
T2 - ISCA 2008, 35th International Symposium on Computer Architecture
Y2 - 21 June 2008 through 25 June 2008
ER -