UVeriESD: An ESD verification tool for SoC design

Keyphrases

• Checkers 100%
• Verification Tool 100%
• SoC Design 100%
• Voltage Drop 66%
• Design Process 33%
• Parasitic Resistance 33%
• Reliability Issues 33%
• Design Flow 33%
• Design Errors 33%
• Verification Method 33%
• Floorplanning 33%
• Netlist 33%
• Power Bus 33%
• Chip Layout 33%
• Discharge Path 33%

Engineering

• Voltage Drop 100%
• System-on-Chip 100%
• Parasitic Resistance 50%
• Redesign 50%
• Floors 50%
• Design Process 50%
• Reliability Issue 50%
• Hazards 50%
• Design Flow 50%
• Chip Layout 50%

Computer Science

• Discharge Path 100%
• Parasitic Resistance 100%