UVeriESD: An ESD verification tool for SoC design

K. Kelvin Hsueh, Sin Hao Ke, Jeffrey Lee, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes an ESD verification methodology that is applied at several points in the design process. By identifying ESD reliability hazards at each step in the design flow, the amount of redesign needed to address ESD reliability issues is greatly reduced. The checker efficiently computes power bus parasitic resistances, allowing it to be used during floor planning when the library is unavailable; it finds the three shortest ESD paths between any two external pads, allowing the checker to be used during IO ring placement before completion of the chip layout; it processes the GDS file and checks the voltage drop between any two ESD devices; it simulates the voltage drop across each ESD device in the discharge path in order to detect ESD design flaws. The ESD checker can be used with or without the actual extracted netlist, i.e., with either a DSPF or a DEF file.

Original languageEnglish (US)
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages53-56
Number of pages4
DOIs
StatePublished - 2008
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: Nov 30 2008Dec 3 2008

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period11/30/0812/3/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'UVeriESD: An ESD verification tool for SoC design'. Together they form a unique fingerprint.

Cite this