Abstract
Compilers for superscalar and VLIW processors must expose sufficient instruction-level parallelism in order to achieve high performance. Compile-time code transformations which expose instruction-level parallelism typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase instruction-level parallelism along the frequent execution scenario at the expense of the less frequent execution sequences. Profile information identifies these important execution sequences in a program. In this paper, two major categories of profile information are studied: control-flow and memory-dependence. Profile-based transformations have been incorporated into the IMPACT compiler. These transformations include global optimization, acyclic global scheduling, and software pipelining. The effectiveness of these profile-based techniques is evaluated for a range of superscalar and VLIW processors.
| Original language | English (US) |
|---|---|
| Title of host publication | Languages and Compilers for Parallel Computing - 5th International Workshop, Proceedings |
| Editors | David Padua, Alex Nicolau, David Gelernter, Utpal Banerjee |
| Publisher | Springer-Verlag |
| Pages | 31-48 |
| Number of pages | 18 |
| ISBN (Print) | 9783540575023 |
| State | Published - Jan 1 1993 |
| Event | IFIP WG 5.7 International Conference on Advances in Production Management Systems, APMS 2017 - Hamburg, Germany Duration: Sep 3 2017 → Sep 7 2017 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 757 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | IFIP WG 5.7 International Conference on Advances in Production Management Systems, APMS 2017 |
|---|---|
| Country | Germany |
| City | Hamburg |
| Period | 9/3/17 → 9/7/17 |
Fingerprint
ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science(all)
Cite this
Using profile information to assist advanced compiler optimization and scheduling. / Chen, W.; Bringmann, R.; Mahlke, S.; Anik, S.; Kiyohara, T.; Warter, N.; Lavery, D.; Hwu, W. M.; Hank, R.; Gyllenhaal, J.
Languages and Compilers for Parallel Computing - 5th International Workshop, Proceedings. ed. / David Padua; Alex Nicolau; David Gelernter; Utpal Banerjee. Springer-Verlag, 1993. p. 31-48 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 757 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Using profile information to assist advanced compiler optimization and scheduling
AU - Chen, W.
AU - Bringmann, R.
AU - Mahlke, S.
AU - Anik, S.
AU - Kiyohara, T.
AU - Warter, N.
AU - Lavery, D.
AU - Hwu, W. M.
AU - Hank, R.
AU - Gyllenhaal, J.
PY - 1993/1/1
Y1 - 1993/1/1
N2 - Compilers for superscalar and VLIW processors must expose sufficient instruction-level parallelism in order to achieve high performance. Compile-time code transformations which expose instruction-level parallelism typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase instruction-level parallelism along the frequent execution scenario at the expense of the less frequent execution sequences. Profile information identifies these important execution sequences in a program. In this paper, two major categories of profile information are studied: control-flow and memory-dependence. Profile-based transformations have been incorporated into the IMPACT compiler. These transformations include global optimization, acyclic global scheduling, and software pipelining. The effectiveness of these profile-based techniques is evaluated for a range of superscalar and VLIW processors.
AB - Compilers for superscalar and VLIW processors must expose sufficient instruction-level parallelism in order to achieve high performance. Compile-time code transformations which expose instruction-level parallelism typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase instruction-level parallelism along the frequent execution scenario at the expense of the less frequent execution sequences. Profile information identifies these important execution sequences in a program. In this paper, two major categories of profile information are studied: control-flow and memory-dependence. Profile-based transformations have been incorporated into the IMPACT compiler. These transformations include global optimization, acyclic global scheduling, and software pipelining. The effectiveness of these profile-based techniques is evaluated for a range of superscalar and VLIW processors.
UR - http://www.scopus.com/inward/record.url?scp=70449836627&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70449836627&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:70449836627
SN - 9783540575023
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 31
EP - 48
BT - Languages and Compilers for Parallel Computing - 5th International Workshop, Proceedings
A2 - Padua, David
A2 - Nicolau, Alex
A2 - Gelernter, David
A2 - Banerjee, Utpal
PB - Springer-Verlag
ER -