## Abstract

The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a synthesis strategy that makes efficient use of this functionality. Traditionally technology mapping algorithms have been developed after the logic architecture has been designed. We follow a dual approach, by focusing on a specific technology mapping algorithm, namely the structural tree-based mapping algorithm, and designing a logic module that can be mapped efficiently by this algorithm. It is known that the tree-based mapping algorithm makes optimal use of a library of functions each of which can be represented by a tree of AND, OR and NOT gates (series-parallel or SP functions). We show how to design a SP function with a minimum number of inputs, that can implement all possible SP functions with a specified number of inputs. For instance, we demonstrate a 7-input SP function that can implement all 4-input SP functions. Mapping results show that, on an average, the number blocks of this function needed to benchmark circuits is 12% less than that for Actel's ACT1 logic modules. Our logic modules show a 4% improvement over ACT1, if the block count is scaled to take into account the number of transistors needed to implement different logic modules.

Original language | English (US) |
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Pages | 31-37 |

Number of pages | 7 |

State | Published - 1996 |

Externally published | Yes |

Event | Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays - Monterey, CA, USA Duration: Feb 11 1996 → Feb 13 1996 |

### Other

Other | Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays |
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City | Monterey, CA, USA |

Period | 2/11/96 → 2/13/96 |

## ASJC Scopus subject areas

- General Computer Science