Unified address translation for memory-mapped SSDs with FlashMap

Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, Karsten Schwan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Applications can map data on SSDs into virtual memory to transparently scale beyond DRAM capacity, permitting them to leverage high SSD capacities with few code changes. Obtaining good performance for memory-mapped SSD content, however, is hard because the virtual memory layer, the file system and the flash translation layer (FTL) perform address translations, sanity and permission checks independently from each other. We introduce FlashMap, an SSD interface that is optimized for memory-mapped SSD-files. FlashMap combines all the address translations into page tables that are used to index files and also to store the FTL-level mappings without altering the guarantees of the file system or the FTL. It uses the state in the OS memory manager and the page tables to perform sanity and permission checks respectively. By combining these layers, FlashMap reduces critical-path latency and improves DRAM caching efficiency. We find that this increases performance for applications by up to 3.32x compared to state-of-the-art SSD file-mapping mechanisms. Additionally, latency of SSD accesses reduces by up to 53.2%.

Original languageEnglish (US)
Title of host publicationISCA 2015 - 42nd Annual International Symposium on Computer Architecture, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages12
ISBN (Electronic)9781450334020
StatePublished - Jun 13 2015
Externally publishedYes
Event42nd Annual International Symposium on Computer Architecture, ISCA 2015 - Portland, United States
Duration: Jun 13 2015Jun 17 2015

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Other42nd Annual International Symposium on Computer Architecture, ISCA 2015
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Hardware and Architecture


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