Understanding the backward slices of performance degrading instructions

Craig B. Zilles, Gurindar S. Sohi

Research output: Contribution to journalConference articlepeer-review


For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early. The backward slice (the subset of the program that relates to the instruction) of these performance degrading instructions, if small compared to the whole dynamic instruction stream, can be pre-executed to hide the instruction's latency. To overcome conservative dependence assumptions that result in large slices, speculation can be used, resulting in speculative slices. This paper provides an initial characterization of the backward slices of L2 data cache misses and branch mispredictions, and shows the effectiveness of techniques, including memory dependence prediction and control independence, for reducing the size of these slices. Through the use of these techniques, many slices can be reduced to less than one tenth of the full dynamic instruction stream when considering the 512 instructions before the performance degrading instruction.

Original languageEnglish (US)
Pages (from-to)172-181
Number of pages10
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - 2000
Externally publishedYes
EventISCA-27: The 27th Annual International Symposium on Computer Architecture - Vancouver, BC, Can
Duration: Jun 10 2000Jun 14 2000

ASJC Scopus subject areas

  • Hardware and Architecture


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