UI-Timer: An ultra-fast clock network pessimism removal algorithm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer, a powerful CNPR algorithm which achieves exact accuracy and ultra-fast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer achieved the best result in terms of accuracy and runtime over all participating timers.

Original languageEnglish (US)
Title of host publication2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages758-765
Number of pages8
EditionJanuary
ISBN (Electronic)9781479962785
DOIs
StatePublished - Jan 5 2015
Event2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - San Jose, United States
Duration: Nov 2 2014Nov 6 2014

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
NumberJanuary
Volume2015-January
ISSN (Print)1092-3152

Other

Other2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014
CountryUnited States
CitySan Jose
Period11/2/1411/6/14

Fingerprint

Clocks
Computer aided design
Networks (circuits)
Data storage equipment
Silicon

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Huang, T. W., Wu, P. C., & Wong, M. D. F. (2015). UI-Timer: An ultra-fast clock network pessimism removal algorithm. In 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers (January ed., pp. 758-765). [7001436] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2015-January, No. January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2014.7001436

UI-Timer : An ultra-fast clock network pessimism removal algorithm. / Huang, Tsung Wei; Wu, Pei Ci; Wong, Martin D.F.

2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers. January. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 758-765 7001436 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2015-January, No. January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, TW, Wu, PC & Wong, MDF 2015, UI-Timer: An ultra-fast clock network pessimism removal algorithm. in 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers. January edn, 7001436, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, no. January, vol. 2015-January, Institute of Electrical and Electronics Engineers Inc., pp. 758-765, 2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, United States, 11/2/14. https://doi.org/10.1109/ICCAD.2014.7001436
Huang TW, Wu PC, Wong MDF. UI-Timer: An ultra-fast clock network pessimism removal algorithm. In 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers. January ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 758-765. 7001436. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; January). https://doi.org/10.1109/ICCAD.2014.7001436
Huang, Tsung Wei ; Wu, Pei Ci ; Wong, Martin D.F. / UI-Timer : An ultra-fast clock network pessimism removal algorithm. 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers. January. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 758-765 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; January).
@inproceedings{4cbb6eda38234fecbc52dfbaf1b7b7c5,
title = "UI-Timer: An ultra-fast clock network pessimism removal algorithm",
abstract = "The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer, a powerful CNPR algorithm which achieves exact accuracy and ultra-fast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer achieved the best result in terms of accuracy and runtime over all participating timers.",
author = "Huang, {Tsung Wei} and Wu, {Pei Ci} and Wong, {Martin D.F.}",
year = "2015",
month = "1",
day = "5",
doi = "10.1109/ICCAD.2014.7001436",
language = "English (US)",
series = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "January",
pages = "758--765",
booktitle = "2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers",
address = "United States",
edition = "January",

}

TY - GEN

T1 - UI-Timer

T2 - An ultra-fast clock network pessimism removal algorithm

AU - Huang, Tsung Wei

AU - Wu, Pei Ci

AU - Wong, Martin D.F.

PY - 2015/1/5

Y1 - 2015/1/5

N2 - The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer, a powerful CNPR algorithm which achieves exact accuracy and ultra-fast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer achieved the best result in terms of accuracy and runtime over all participating timers.

AB - The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer, a powerful CNPR algorithm which achieves exact accuracy and ultra-fast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer achieved the best result in terms of accuracy and runtime over all participating timers.

UR - http://www.scopus.com/inward/record.url?scp=84936884172&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84936884172&partnerID=8YFLogxK

U2 - 10.1109/ICCAD.2014.7001436

DO - 10.1109/ICCAD.2014.7001436

M3 - Conference contribution

AN - SCOPUS:84936884172

T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

SP - 758

EP - 765

BT - 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

ER -