Turbo decoder architectures for low-density parity-check codes

Keyphrases

• AWGN Channel 25%
• Convergence Behavior 25%
• Decoder 25%
• Decoding Latency 25%
• Decoding Schedules 50%
• Direct Sum 25%
• Encoder-decoder Architecture 100%
• Fast Convergence 25%
• Low Density Code 75%
• Low-density Parity-check Codes 100%
• Memory Requirements 25%
• Phase Schedule 25%
• Reduced Memory 25%
• Single Parity Check 25%
• Soft Output 25%
• Turbo Decoder 100%
• Turbo Decoding 75%

Engineering

• Memory Requirement 50%
• Parity Check Code 100%
• Soft Output 50%