Turbo decoder architectures for low-density parity-check codes

Mohammad M. Mansour, Naresh R Shanbhag

Research output: Contribution to conferencePaper

Abstract

Turbo decoding of low-density parity-check (LDPC) and generalized low-density (GLD) codes and the corresponding decoder architectures are considered. A regular (c, r)-LDPC code of length n is viewed as the intersection of c interleaved super-codes where each super-code is the direct sum of n/r independent single parity-check sub-codes. Extensions to GLD codes simply utilize more powerful sub-codes. The turbo decoding schedule is employed to decode LDPC and GLD codes using constituent soft-input soft-output (SISO) decoders that communicate through c interleaves. The proposed schedule exhibits a faster convergence behavior, and hence lower decoding latency, than the commonly employed two-phase schedule, and has a reduced memory requirement that is a function of the number of super-codes. The performance of the turbo decoding schedule is evaluated through simulations over an AWGN channel.

Original languageEnglish (US)
Pages1383-1388
Number of pages6
StatePublished - Dec 1 2002
EventGLOBECOM'02 - IEEE Global Telecommunications Conference - Taipei, Taiwan, Province of China
Duration: Nov 17 2002Nov 21 2002

Other

OtherGLOBECOM'02 - IEEE Global Telecommunications Conference
CountryTaiwan, Province of China
CityTaipei
Period11/17/0211/21/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

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  • Cite this

    Mansour, M. M., & Shanbhag, N. R. (2002). Turbo decoder architectures for low-density parity-check codes. 1383-1388. Paper presented at GLOBECOM'02 - IEEE Global Telecommunications Conference, Taipei, Taiwan, Province of China.