Trimaran: An infrastructure for research in instruction-level parallelism

Lakshmi N. Chakrapani, John Gyllenhaal, Wen Mei W. Hwu, Scott A. Mahlke, Krishna V. Palem, Rodric M. Rabbah

Research output: Contribution to journalConference article

Abstract

Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor architecture supporting novel features such as predication, control and data speculation and compiler controlled management of the memory hierarchy. Trimaran also consists of a full suite of analysis and optimization modules, as well as a graph-based intermediate language. Optimizations and analysis modules can be easily added, deleted or bypassed, thus facilitating compiler optimization research. Similarly, computer architecture research can be conducted by varying the HPL-PD machine via the machine description language HMDES. Trimaran also provides a detailed simulation environment and a flexible performance monitoring environment that automatically tracks the machine as it is varied.

Original languageEnglish (US)
Pages (from-to)32-41
Number of pages10
JournalLecture Notes in Computer Science
Volume3602
StatePublished - Oct 19 2005
Event17th International Workshop on Languages and Compilers for High Performance Computing, LCPC 2004 - West Lafayette, IN, United States
Duration: Sep 22 2004Sep 24 2004

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ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Chakrapani, L. N., Gyllenhaal, J., Hwu, W. M. W., Mahlke, S. A., Palem, K. V., & Rabbah, R. M. (2005). Trimaran: An infrastructure for research in instruction-level parallelism. Lecture Notes in Computer Science, 3602, 32-41.