The stochastic sensor network-on-chip (SSNOC) was recently proposed as an effective computational paradigm for jointly achieving energy-efficiency and robustness in nanoscale processes. In this paper, we study the trends in energy-efficiency and robustness exhibited by an SSNOC architecture as the feature size scales from 130nm to 32nm for a PN-code acquisition application. The conventional architecture exhibits a 3 orders-of-magnitude loss in detection probability Pdet due to process variations in the 130nm and smaller technology nodes. At the 130nm and 90nm nodes, the proposed SS-NOC architecture recovers from this performance loss, and exhibits a 2 orders-of-magnitude smaller variation in Pdet compared to the conventional architecture. However, for the 65nm and 45nm technology nodes, the SSNOC architecture with assistance from circuit level techniques such as adaptive body bias (ABB) and adaptive supply voltage (ASV) shows a 2-3 order-of-magnitude better detection performance. In addition, the SSNOC architecture with ABB/ASV achieves 22% to 31% energy savings. For the 32nm node, the current version of SSNOC with ABB/ASV is not robust enough and thus motivates the need to explore even more powerful versions of SSNOC.